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page 1 of 13 document no. 70-0243-06 www.psemi.com ?2008-2009 peregrine semiconductor corp. all rights reserved. the pe43701 is a harp ? -enhanced, high linearity, 7-bit rf digital step attenuator (dsa). this highly versatile dsa covers a 31.75 db attenuation range in 0.25 db steps. the peregrine 50 ? rf dsa provides a parallel or serial- addressable cmos control interface. it maintains high attenuation accuracy over frequency and temperature and exhibits very low insertion loss and low power consumption. performance does not change with vdd due to on-board regulator. this next generation peregrine dsa is available in a 5x5 mm 32-lead qfn footprint. the pe43701 is manufactured on peregrine?s ultracmos? process, a patented variation of silicon-on-insulator (soi) technology on a sapphire substrate, offering the performance of gaas with the economy and integration of conventional cmos. product specification 50 ? rf digital attenuator 7-bit, 31.75 db, 9 khz - 4.0 ghz product description figure 2. functional schematic diagram pe43701 features ? harp?-enhanced ultracmos? device ? attenuation: 0.25 db steps to 31.75 db ? high linearity: typical +59 dbm iip3 ? excellent low-frequency performance ? 3.3 v or 5.0 v power supply voltage ? fast switch settling time ? programming modes: ? direct parallel ? latched parallel ? serial-addressable: program up to eight addresses 000 - 111 ? high-attenuation state @ power-up (pup) ? cmos compatible ? no dc blocking capacitors required ? packaged in a 32-lead 5x5x0.85 mm qfn figure 1. package type 32-lead 5x5x0.85 mm qfn package control logic interface rf input rf output switched attenuator array serial in le clk a0 a1 a2 parallel control 7 p/s logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe43701 page 2 of 13 ?2008-2009 peregrine semiconductor corp. all rights reserved. document no. 70-0243-06 ultracmos? rfic solutions -0.25 0.00 0.25 0.50 0 4 8 121620242832 attenuation setting (db) step error (db) 200 mhz 900 mhz 1800 mhz 2200 mhz 3000 mhz table 1. electrical specifications @ +25c, v dd = 3.3 v or 5.0 v figure 5. 0.25 db major state bit error figure 3. 0.25 db step error vs. frequency* performance plots 900 mhz 1800 mhz 2200 mhz 3800 mhz 5 1015202530 035 5 10 15 20 25 30 0 35 attenuation state attenuation db 0.25-db pe43701 attenuation figure 4. 0.25db attenuation vs. attenuation state parameter test conditions frequency min typical max units frequency range 9 khz 4.0 ghz attenuation range 0.25 db step 0 ? 31.75 db insertion loss 9 khz 4 ghz 1.9 2.4 db attenuation error 0 db - 7.75 db attenuation settings 8 db - 31.75 db attenuation settings 0 db - 31.75 db attenuation settings 9 khz < 3 ghz 9 khz < 3 ghz 3 ghz 4 ghz (0.2+1.5%) (0.15+4%) (0.25+4.5%) db db db return loss 9 khz - 4 ghz 18 db relative phase all states 9 khz - 4 ghz 44 deg p1db (note 1) input 20 mhz - 4 ghz 30 32 dbm iip3 two tones at +18 dbm, 20 mhz spacing 20 mhz - 4 ghz 59 dbm typical spurious value 1mhz -110 dbm video feed through 10 mvpp switching time 50% dc ctrl to 10% / 90% rf 650 ns rf trise/tfall 10% / 90% rf 400 ns settling time rf settled to within 0.05 db of final value rbw = 5 mhz, averaging on. 4 25 s * monotonicity is held so long as step-error does not cross below -0.25 figure 6. 0.25 db attenuation error vs. frequency note 1. please note maximum operating pin (50 ? ) of +23dbm as shown in table 3. -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0 1000 2000 3000 4000 frequency (mhz) attenuation error (db) 0.25db state 0.5db state 1db state 2db state 4db state 8db state 16db state 31.75db state -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 attenuation setting (db) attenuation error (db) 200 mhz 900 mhz 1800 mhz 2200 mhz 3000 mhz 4000 mhz logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe43701 page 3 of 13 document no. 70-0243-06 www.psemi.com ?2008-2009 peregrine semiconductor corp. all rights reserved. -70 -60 -50 -40 -30 -20 -10 0 01234567 89 frequency (ghz) return loss (db) 0db 0.25db 0.5db 1db 2db 4db 8db 16db 31.75db -40 -35 -30 -25 -20 -15 -10 -5 0 0123456789 frequency (ghz) return loss (db) -40c 25c 85c figure 9. output return loss vs. attenuation: t = +25c figure 7. insertion loss vs. temperature figure 8. input return loss vs. attenuation: t = +25c figure 10. input return loss vs. temperature: 16db state figure 11. output return loss vs. temperature: 16db state figure 12. relative phase vs. frequency -5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 frequency (ghz) insertion loss (dbm) -40c +25c +85c -60 -50 -40 -30 -20 -10 0 0123456789 frequency (ghz) return loss (db) 0db 0.25db 0.5db 1db 2db 4db 8db 16db 31.75db -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 0123456789 frequency (ghz) return loss (db) -40c 25c 85c 0 20 40 60 80 100 120 012345678 frequency (ghz) relative phase error (deg) 0db 0.25db 0.5db 1db 2db 4db 8db 16db 31.75db logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe43701 page 4 of 13 ?2008-2009 peregrine semiconductor corp. all rights reserved. document no. 70-0243-06 ultracmos? rfic solutions 30 35 40 45 50 55 60 65 70 0 500 1000 1500 2000 2500 3000 3500 4000 4500 frequency (mhz) input ip3 (dbm ) 0db 0.25db 0.5db 1db 2db 4db 8db 16db 31.75db -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 attenuation setting (db) attenuation error (db) +25 c -40 c +85 c -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 attenuation setting (db) attenuation error (db) +25 c -40 c +85 c 0 5 10 15 20 25 30 35 -40-200 20406080 temperature (deg. c) phase (deg) 900 mhz 1800 mhz 3000 mhz figure 15. attenuation error vs. attenuation setting: 1800 mhz figure 13. relative phase vs. temperature: 31.75db state figure 14. attenuation error vs. attenuation figure 16. attenuation error vs. attenuation setting: 3000 mhz figure 17. input ip3 vs. frequency -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 attenuation setting (db) attenuation error (db) +25 c -40 c +85 c logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe43701 page 5 of 13 document no. 70-0243-06 www.psemi.com ?2008-2009 peregrine semiconductor corp. all rights reserved. 8 7 6 5 4 3 2 1 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 16 15 14 13 12 11 10 9 exposed solder pad nc v dd p/s a0 gnd gnd rf1 gnd gnd gnd gnd gnd gnd gnd gnd gnd clk le a1 a2 gnd gnd rf2 gnd c0.25 c0.5 c1 c2 c4 c8 c16 si electrostatic discharge (esd) precautions when handling this ultracmos? device, observe the same precautions that you would use with other esd- sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the specified rating. exposed solder pad connection the exposed solder pad on the bottom of the package must be grounded for proper device operation. figure 18. pin configuration (top view) latch-up avoidance unlike conventional cmos devices, ultracmos? devices are immune to latch-up. switching frequency the pe43701 has a maximum 25 khz switching rate. switching rate is defined to be the speed at which the dsa can be toggled across attenuation states. pin no. pin name description 1 n/c no connect 2 v dd power supply pin 3 p ? /s serial/parallel mode select 4 a0 address bit a0 (lsb) 5, 6, 8-17, 19, 20 gnd ground 7 rf1 rf1 port 18 rf2 rf2 port 21 a2 address bit a2 22 a1 address bit a1 23 le latch enable input 24 clk serial interface clock input 25 si serial interface input 26 c16 attenuation control bit, 16 db 27 c8 attenuation control bit, 8 db 28 c4 attenuation control bit, 4 db 29 c2 attenuation control bit, 2 db 30 c1 attenuation control bit, 1 db 31 c0.5 attenuation control bit, 0.5 db 32 c0.25 attenuation control bit, 0.25 db paddle gnd ground for proper operation table 2. pin descriptions moisture sensitivity level the moisture sensitivity level rating for the pe43701 in the 5x5 qfn package is msl1. logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe43701 page 6 of 13 ?2008-2009 peregrine semiconductor corp. all rights reserved. document no. 70-0243-06 ultracmos? rfic solutions 0.0 5.0 10.0 15.0 20.0 25.0 30.0 1.0e+03 1.0e+04 1.0e+05 1.0e+06 1.0e+07 1.0e+08 1.0e+09 hz pin dbm table 3. operating ranges table 4. absolute maximum ratings exceeding absolute maximum ratings may cause permanent damage. operation should be restricted to the limits in the operating ranges table. operation between operating range maximum and absolute maximum for extended periods may reduce reliability. symbol parameter/conditions min max units v dd power supply voltage -0.3 6.0 v v i voltage on any digital input -0.3 5.8 v t st storage temperature range -65 150 c v esd esd voltage (hbm) 1 esd voltage (machine model) 500 100 v v p in input power (50 ? ) 1 hz 20 mhz 20 mhz 4 ghz see fig. 19 +23 dbm dbm parameter min typ max units v dd power supply voltage 3.0 3.3 v i dd power supply current 70 350 a digital input high 2.6 5.5 v p in input power (50 ? ): 1 hz 20 mhz 20 mhz 4 ghz see fig. 19 +23 dbm dbm t op operating temperature range -40 25 85 c digital input low 0 1 v digital input leakage 1 15 a v dd power supply voltage 5.0 5.5 v note 1. input leakage current per control pin note: 1. human body model (hbm, mil_std 883 method 3015.7) figure 19. maximum power handling capability: z 0 = 50 ? logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe43701 page 7 of 13 document no. 70-0243-06 www.psemi.com ?2008-2009 peregrine semiconductor corp. all rights reserved. table 6. latch and clock specifications table 5. control voltage state bias condition low 0 to +1.0 vdc at 2 a (typ) high +2.6 to +5 vdc at 10 a (typ) table 7. parallel truth table table 10. serial-addressable register map latch enable function 0 shift register clocked contents of shift register transferred to attenuator core shift clock x parallel control setting attenuation setting rf1-rf2 d6 d5 d4 d3 d2 d1 d0 l l l l l l l reference i.l. l l l l l l h 0.25 db l l l l l h l 0.5 db l l l l h l l 1 db l l l h l l l 2 db l l h l l l l 4 db l h l l l l l 8 db h l l l l l l 16 db h h h h h h h 31.75 db address word address setting a7 (msb) a6 a5 a4 a3 a2 a1 a0 x x x x x l l l 000 x x x x x l l h 001 x x x x x l h l 010 x x x x x l h h 011 x x x x x h l l 100 x x x x x h l h 101 x x x x x h h l 110 x x x x x h h h 111 table 8. address word truth table attenuation word d7 d6 d5 d4 d3 d2 d1 d0 (lsb) l l l l l l l l reference i.l. l l l l l l l h 0.25 db l l l l l h l l 1 db l l l l h l l l 2 db l l l h l l l l 4 db l l h l l l l l 8 db l h l l l l l l 16 db l h h h h h h h 31.75 db attenuation setting rf1-rf2 l l l l l l h l 0.5 db table 9. attenuation word truth table q15 q14 q13 q12 q11 q10 a7 a6 a5 a4 a3 a2 q9 q8 q7 q6 q5 q4 a1 a0 *d7 d6 d5 d4 q3 q2 q1 q0 d3 d2 d1 d0 address word attenuation word lsb (first in) msb (last in) bits can either be set to logic high or logic low attenuation word is derived directly from the attenuation value. for example, to program the 18.25 db state at address 3: address word: xxxxx011 attenuation word: multiply by 4 and convert to binary 4 * 18.25 db 73 01001001 serial input: xxxxx01101001001 *d7 must be set to logic low logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe43701 page 8 of 13 ?2008-2009 peregrine semiconductor corp. all rights reserved. document no. 70-0243-06 ultracmos? rfic solutions programming options parallel/serial-addressable selection either a parallel or serial-addressable interface can be used to control the pe43701. the p ? /s bit provides this selection, with p ? /s=low selecting the parallel interface and p ? /s=high selecting the serial interface. parallel mode interface the parallel interface consists of seven cmos- compatible control lines that select the desired attenuation state, as shown in table 7 . the parallel interface timing requirements are defined by fig. 21 (parallel interface timing diagram), table 12 (parallel interface ac characteristics), and switching speed ( table 1 ). for latched -parallel programming the latch enable (le) should be held low while changing attenuation state control values, then pulse le high to low ( per fig. 21 ) to latch new attenuation state into device. for direct parallel programming, the latch enable (le) line should be pulled high. changing attenuation state control values will c hange device state to new attenuation. direct mode is ideal for manual control of the device (using hardwire, switches, or jumpers). serial-addressable interface the serial-addressable interface is a 16-bit serial-in, parallel-out shift register buffered by a transparent latch. the 16-bits make up two words comprised of 8-bits each. the first word is the attenuation word, which controls the state of the dsa. the second word is the address word, which is compared to the static (or programmed) logical states of the a0, a1 and a2 digital inputs. if there is an address match, the dsa changes state; otherwise its current state will remain unchan ged. fig. 20 illustrates a example timing diagram for programming a state. it is recommended that all parallel control inputs be grounded when the dsa is used in serial mode. the serial-addressable interface is controlled using three cmos-compatible signals: serial-in (si), clock (clk), and latch enable (le). the si and clk inputs allow data to be serially entered into the shift register. serial data is clocked in lsb first, beginning with the attenuation word. the shift register must be loaded while le is held low to prevent the attenuator value from changing as data is entered. the le input should then be toggled high and brought low again, latching the new data into the dsa. address word and attenuation word truth tables are listed in table 8 & table 9 , respectively. a programming example of the serial-addressable register is illustrated in table 10 . the serial-addressable timing diagram is illustrated in fig. 20. power-up control settings the pe43701 will always initialize to the maximum attenuation setting (31.75 db) on power-up for both the serial-addressable and latched-parallel modes of operation and will remain in this setting until the user latches in the next programming word. in direct- parallel mode, the dsa can be preset to any state within the 31.75 db range by pre-setting the parallel control pins prior to power-up. in this mode, there is a 400-s delay between the time the dsa is powered-up to the time the desired state is set. during this power-up delay, the device attenuates to the maximum attenuation setting (31.75 db) before defaulting to the user defined state. if the control pins are left floating in this mode during power-up, the device will default to the minimum attenuation setting (insertion loss state). dynamic operation between serial-addressable and parallel programming modes is possible. if the dsa powers up in serial-addressable mode ( p ?/ s = high), all the parallel control inputs di[6:0] must be set to logic low. prior to toggling to parallel mode, the dsa must be programmed serially to ensure d[7] is set to logic low. if the dsa powers up in either latched or direct- parallel mode, all parallel pins di[6:0] must be set to logic low prior to toggling to serial-addressable mode ( p ? /s = high), and held low until the dsa has been programmed serially to ensure bit d[7] is set to logic low. the sequencing is only required once on power- up. once completed, the dsa may be toggled between serial-addressable and parallel programming modes at will. logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe43701 page 9 of 13 document no. 70-0243-06 www.psemi.com ?2008-2009 peregrine semiconductor corp. all rights reserved. table 12. parallel and direct interface ac characteristics table 11. serial-addressable interface ac characteristics note: f clk is verified during the functional pattern test. serial- addressable programming sections of the functional pattern are clocked at 10 mhz to verify fclk specification. v dd = 3.3 or 5.0 v, -40 c < t a < 85 c, unless otherwise specified v dd = 3.3 or 5.0 v, -40 c < t a < 85 c, unless otherwise specified figure 20. serial-addressable timing diagram figure 21. latched-parallel/direct-parallel timing diagram symbol parameter min max unit f clk serial clock frequency - 10 mhz t clkh serial clock high time 30 - ns t clkl serial clock low time 30 - ns t lesu last serial clock rising edge setup time to latch enable rising edge 10 - ns t lepw latch enable min. pulse width 30 - ns t sisu serial data setup time 10 - ns t sih serial data hold time 10 - ns t disu parallel data setup time 100 - ns t dih parallel data hold time 100 - ns t asu address setup time 100 - ns t ah address hold time 100 - ns t pssu parallel/serial setup time 100 - ns t psh parallel/serial hold time 100 - ns t pd digital register delay (internal) - 10 ns symbol parameter min max unit t lepw latch enable minimum pulse width 30 - ns t disu parallel data setup time 100 - ns t dih parallel data hold time 100 - ns t pssu parallel/serial setup time 100 - ns t psih parallel/serial hold time 100 - ns t pd digital register delay (internal) - 10 ns t dipd digital register delay (internal, direct mode only) - 5 ns valid t disu t dih di[6:0] le p/s t pssu t psh t lepw valid do[6:0] t dipd t pd a[2] a[1] a[0] t sisu t clkl t le pw t sih t clk h si clk le p/s t lesu t pssu t psih valid t asu add[2:0] t aih do[6:0] valid di[6:0] t pd t dis u t dih d[6] d[5] d[4] d[3] d[2] d[1] d[0] *d[7] *d[7] must be set to logic low bits can either be set to logic high or logic low logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe43701 page 10 of 13 ?2008-2009 peregrine semiconductor corp. all rights reserved. document no. 70-0243-06 ultracmos? rfic solutions evaluation kit the digital attenuator evaluation kit board was designed to ease customer evaluation of the pe43701 digital step attenuator. direct-parallel programming procedure for automated direct-parallel programming, connect the test harness provided with the evk from the parallel port of the pc to the j1 & serial header pin and set the d0-d6 sp3t switches to the ?middle? toggle position. position the parallel/ serial ( p ? /s) select switch to the parallel (or left) position. the evaluation software is written to operate the dsa in either parallel or serial- addressable mode. ensure that the software is set to program in direct-parallel mode. using the software, enable or disable each setting to the desired attenuation state. the software automatically programs the dsa each time an attenuation state is enabled or disabled. for manual direct-parallel programming, disconnect the test harness provided with the evk from the j1 and serial header pins. position the parallel/serial ( p ? /s) select switch to the parallel (or left) position. the le pin on the serial header must be tied to v dd . switches d0-d6 are sp3t switches which enable the user to manually program the parallel bits. when any input d0-d6 is toggled ?up?, logic high is presented to the parallel input. when toggled ?down?, logic low is presented to the parallel input. setting d0-d6 to the ?middle? toggle position presents an open, which forces an on-chip logic low. table 9 depicts the parallel programming truth table and fig. 21 illustrates the parallel programming timing diagram. latched-parallel programming procedure for automated latched-parallel programming, the procedure is identical to the direct-parallel method. the user only must ensure that latched-parallel is selected in the software. for manual latched-parallel programming, the procedure is identical to direct-parallel except now the le pin on the serial header must be logic low as the parallel bits are applied. the user must then pulse le from 0v to v dd and back to 0v to latch the programming word into the dsa. le must be logic low prior to programming the next word. figure 22. evaluation board layout peregrine specification 101-0312 serial-addressable programming procedure position the parallel/serial ( p ? /s) select switch to the serial (or right) position. prior to programming, the user must define an address setting using the add header pin. jump the middle pins on the add header a0-a2 (or lower) row of pins to set logic high, or jump the middle pins to the upper row of pins to set logic low. if the add pins are left open, then 000 become the default address. the evaluation software is written to operate the dsa in either parallel or serial-addressable mode. ensure that the software is set to program in serial-addressable mode. using the software, enable or disable each setting to the desired attenuation state. the software automatically programs the dsa each time an attenuation state is enabled or disabled. note: reference fig. 23 for evaluation board schematic logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe43701 page 11 of 13 document no. 70-0243-06 www.psemi.com ?2008-2009 peregrine semiconductor corp. all rights reserved. figure 24. package drawing qfn 5x5 mm a max 0.900 nom 0.850 min 0.800 figure 23. evaluation board schematic peregrine specification 102-0381 note: capacitors c1-c8, c13, & c14 may be omitted. on the pe43701 pin 20 (shown as v ss ) must be grounded. logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe43701 page 12 of 13 ?2008-2009 peregrine semiconductor corp. all rights reserved. document no. 70-0243-06 ultracmos? rfic solutions table 13. ordering information figure 26. marking specifications 43701 yyww zzzzz yyww = date code zzzzz = last five digits of lot number figure 25. tape and reel drawing order code part marking description package shipping method pe43701mli 43701 pe43701 g - 32qfn 5x5mm-75a green 32-lead 5x5mm qfn bulk or tape cut from reel pe43701mli-z 43701 pe43701 g ? 32qfn 5x5mm-3000c green 32-lead 5x5mm qfn 3000 units / t&r ek43701-01 43701 pe43701 g ? 32qfn 5x5mm-ek evaluation kit 1 / box device orientation in tape top of device pin 1 tape feed direction logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com
product specification pe43701 page 13 of 13 document no. 70-0243-06 www.psemi.com ?2008-2009 peregrine semiconductor corp. all rights reserved. sales offices the americas peregrine semiconductor corporation 9380 carroll park drive san diego, ca 92121 tel: 858-731-9400 fax: 858-731-9499 europe peregrine semiconductor europe batiment maine 13-15 rue des quatre vents f-92380 garches, france tel: +33-1-4741-9173 fax : +33-1-4741-9173 for a list of representatives in your area, please refer to our web site at: www.psemi.com data sheet identification advance information the product is in a formative or design stage. the data sheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification the data sheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification the data sheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify customers of the intended changes by issuing a cnf (customer notification form). the information in this data sheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liabilit y for damages, including consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, and utsi are registered trademarks and ultracmos, harp, multiswitch and dune are trademarks of peregrine semiconductor corp. high-reliability and defense products americas san diego, ca, usa phone: 858-731-9475 fax: 848-731-9499 europe/asia-pacific aix-en-provence cedex 3, france phone: +33-4-4239-3361 fax: +33-4-4239-7227 peregrine semiconductor, asia pacific (apac) shanghai, 200040, p.r. china tel: +86-21-5836-8276 fax: +86-21-5836-7652 peregrine semiconductor, korea #b-2607, kolon tripolis, 210 geumgok-dong, bundang-gu, seongnam-si gyeonggi-do, 463-943 south korea tel: +82-31-728-3939 fax: +82-31-728-3940 peregrine semiconductor k.k., japan teikoku hotel tower 10b-6 1-1-1 uchisaiwai-cho, chiyoda-ku tokyo 100-0011 japan tel: +81-3-3502-5211 fax: +81-3-3502-5213 logo updated under non-rev change. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com

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